Power consumption is becoming an increasing concern in the design of integrated circuits (ICs), particularly for very large scale integration (VLSI) chip design. Increases in power consumption are outpacing the advantages of advances in scaling in silicon technologies, and the benefits of reducing power supply voltages. To address this concern, many computer-aided design (CAD) tools have been developed to measure or estimate power consumption in VLSI designs. These tools for example provides for system level design, verification, analysis and simulated testing of register-transfer logic (RTL), gates and physical layout structures. In one example, certain CAD software may further perform transistor-level timing analysis of electronic designs. The estimated power consumption is employed to help designers meet target power parameters and ultimately facilitate design convergence.
Power efficiency within the electronic design is important because, among other reasons, power may often be traded for increased performance. Due to the increased complexity of electronic designs often exceeding one billion components, optimizing power consumption within the circuit design has become increasingly difficult. Power consumption within the electronic design may derive from several sources, including dynamic switching power of capacitors, DC currents including leakage from diodes, and crossover currents in static complimentary metal oxide semiconductor (CMOS) logic using field effect transistors (FETs), such as metal-oxide silicon field effect transistors (MOSFETs).
Techniques used to estimate power consumption in VLSI chip designs can be divided into two general groups: simulation-based techniques and statistics-based techniques. Existing simulation-based approaches are employed for performance and power consumption analysis of VLSI designs. These simulation approaches tend to be highly dependent on the input patterns (or input vectors) used to stimulate the circuit model. That is, the power estimation tool usually requires varying input patterns designed specifically for power estimation. Optimization techniques are used to optimize the performance, size and power consumption of a design. Power estimation for both the simulation and optimization techniques is computationally expensive and time consuming.